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80CH SEGMENT DRIVER FOR DOT MATRIX LCD
S6B2104
INTRODUCTION
The S6B2104 is a LCD driver IC, which is fabricated by low power CMOS high voltage process technology. This device consists of 80-bit bi-directional shift register, 80-bit data latch and 80 bit driver.
FEATURES * * * * * Power supply voltage: +5V 10%, +3V 10% Supply voltage for display: 6 to 28V (VDD-VEE) Parallel data processing (4 bit) Applicable LCD duty: 1/64 to 1/256 Interface Drivers COM S6B0086 * * SEG (cascade) Other S6B2104
High voltage CMOS process 100 QFP or bare chip available
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S6B2104
80CH SEGMENT DRIVER FOR DOT MATRIX LCD
BLOCK DIAGRAM
V1 V3 V4 VEE
80 bit 4- Level Driver
M DISPOFFB
80 bit Level Shifter
CL1
80 bit Data Latch
D0 D1 D2 D3
20 x 4 bit Bidirectional Register
S78 S79 S80
S1 S2 S3
SHL
CL2 EIB
Shift CL Power Down Function
VDD VSS EOB
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PIN CONFIGURATION
80CH SEGMENT DRIVER FOR DOT MATRIX LCD
SC31 SC32 SC33 SC34 SC35 SC36 SC37 SC38 SC39 SC40 SC41 SC42 SC43 SC44 SC45 SC46 SC47 SC48 SC49 SC50 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
S6B2104
SC51 SC52 SC53 SC54 SC55 SC56 SC57 SC58 SC59 SC60 SC61 SC62 SC63 SC64 SC65 SC66 SC67 SC68 SC69 SC70 SC71 SC72 SC73 SC74 SC75 SC76 SC77 SC78 SC79 SC80 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 EIB CL1 NC CL2 D0 D1 D2 D3 VSS SHL VDD DISPOFFB M NC V1 V3 V4 VEE NC EOB SC30 SC29 SC28 SC27 SC26 SC25 SC24 SC23 SC22 SC21 SC20 SC19 SC18 SC17 SC16 SC15 SC14 SC13 SC12 SC11 SC10 S9 S8 S7 S6 S5 S4 S3 S2 S1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
S6B2104
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S6B2104
80CH SEGMENT DRIVER FOR DOT MATRIX LCD
MAXIMUM ABSOLUTE LIM IT
Characteristic Operating voltage Driver supply voltage Input voltage Operating temperature Storage temperature Symbol VDD VLCD VIN TOPR TSTG Value -0.3 - 6.0 0 - 30 -0.3 - VDD +0.3 -30 - +85 -55 - +150 C Unit V
Voltage greater than above may result in damage to the circuit.
VDD (V1) VDD-VEE V3 To LCD Panel S1 - S80 +V
S6B2104
V4 VEE -V V1 > V3 > V4 > VEE V1 < VDD
VSS
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80CH SEGMENT DRIVER FOR DOT MATRIX LCD
S6B2104
ELECTRICAL CHARACTER ISTICS DC Characteristics (VDD = 2.7 to 5.5V, VSS = 0V, Ta = -30 to +85C, CL = 15pF) Characteristics Operating voltage Driver supply voltage Input voltage (1) Symbol VDD VLCD VIH VIL Output voltage (2) VOH VOL Input leakage current 1 (1) Input leakage current 2 (3) On resistance (4) Supply current IIL1 IIL2 RON ISTB IDD IOH = -0.4mA IOL = 0.4mA VIN = VDD to VSS VIN = VDD to VEE ION = 100A fCL2 = 1MHz, fCL2 = 19.2kHz, fM = 40Hz, VLCD = 26V IEE No Load VDD = 5.5V (5) VDD = 5.5V (6) VDD = 2.7V (6) VDD = 5.5V (7) Condition VLCD = VDD - VEE Min 2.7 6 0.8VDD 0 VDD-0.4 -1 -25 Typ 2 150 Max 5.5 28 0.2VDD 0.4 1 25 4 200 3 1 500 k A mA mA A A V Unit V
NOTES: 1. Applied to CL1, CL2, EIB, EOB, D0 to D3, SHL, DISPOFFB, M pin. 2. EIB, EOB pin 3. V1, V3, V4 pin 4. VDD-VEE = 26V(VDD = 3V), VEE = 28V(VDD = 5V), V1 = VDD, V3 = VDD-2/10(VDD-VEE), V4 = VEE+2/10(VDD-VEE), S1 to S80 pin 5. Display data pattern: 0000, Current from VDD to VSS when the display data is not processing (SHL = VSS, D0 to D3 = VSS, DISPOFFB = VDD, M = VSS) 6. Display data pattern: 1010, Current from VDD to VSS when the display data is processing 7. Display data pattern: 1010, Current on VEE pin
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S6B2104
80CH SEGMENT DRIVER FOR DOT MATRIX LCD
AC Characteristics (VDD = +5V 10%, VSS = 0V, Ta = -30 to +85 C, CL = 15pF) Characteristic Clock cycle time Clock pulse width Clock rise/fall time Data set-up time Data hold time Clock set-up time1 Clock set-up time2 Clock hold time Propagation delay time Symbol tCYC tW tR/tF tDS tDH TCS1 TCS2 tCH tPHL tPSU Condition Duty = 50% EOB output EIB output EIB, EOB set-up time EOB input EIB input (VDD = +3V 10%, VSS = 0V, Ta = -30 to +85C, CL = 15pF) Characteristic Clock cycle time Clock pulse width Clock rise/fall time Data set-up time Data hold time Clock set-up time1 Clock set-up time2 Clock hold time Propagation delay time Symbol tCYC tW tR/tF tDS tDH TCS1 tCS2 tCH tPHL tPSU Condition Duty = 50% EOB output EIB output EIB, EOB set-up time EOB input EIB input 65 65 Min 250 95 50 50 80 15 120 155 155 Typ Max 30 Unit ns 30 30 Min 125 45 30 30 80 10 80 Typ Max 30 80 80 Unit ns
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80CH SEGMENT DRIVER FOR DOT MATRIX LCD
S6B2104
Timing Chara cteristics
tw 0.8VDD tDS D0 to D3 0.8VDD
tF
tw
tw 0.8VDD
CL2
0.2VDD 0.2VDD tDH 0.2VDD tCS1
tCS2 CL1
tCH 0.8VDD tw tR 0.2VDD tF
CL2
1
2 ~ ~
19
0.2VDD 20
0.8VDD
CL1 ~ ~ tPHL ~ ~ EOB, EIB (output) EIB, EOB (input) 0.2VDD tPUS ~ ~
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S6B2104
80CH SEGMENT DRIVER FOR DOT MATRIX LCD
PIN DESCRIPTION
Table 1. Pin Description Pin No VDD (40) VSS (42) VEE (33) V1, V3, V4 (34-36) S1-S80 (1-30, 51-100) I Negative supply voltage LCD driver output voltage level LCD driver output I/O Name 0V (GND) For LCD drive circuit Bias supply voltage terminals to drive the LCD. Bias voltage divided by the resistance is usually used as supply voltage source. (refer to note 1) Display data output pin which corresponds to the respective latch contents. One of V1, V3, V4 and VEE is selected as a display driving voltage source according to the combination of the latched data level and M signal (refer to note 2) Clock pulse input for the 4 bit parallel shift register. The data is shifted to 80 bit shift register at the falling edge of the clock pulse. The clock pulse, which was input when the enable bit (EIB/EOB) is not active condition, is invalid. Alternate signal input pin for LCD driving. Normal frame inversion signal is input The signal for latching the shift register contents is input to this terminal. CL1 pulse "H" level initializes power-down function block. Control input pin for display data output level (S1S80). V1 level is output from S1-S80 terminal during "L" level input. LCD becomes non-selected by V1 level output from every output of segment drivers and every output of common drivers. EOB and EIB can be used as either input terminal or output terminal according to the condition of SHL. The shifting direction of each data, D0-D3, the I/O condition of EOB and EIB, and the condition of SHL are described in the table below. (refer to note 3). Function For logical circuit (+5V 10%, +3V 10%) Power Supply Power Interface
Power Operating voltage
O
LCD
CL2 (47)
I
Data shift clock
Controller
M (38) CL1 (49)
I I
Alternate signal for LCD driver output Data latch clock
Controller Controller
DISPOFFB (39)
I
Output level control (Display off)
Controller
SHL (41)
I
Data shift control
VDD/VSS
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80CH SEGMENT DRIVER FOR DOT MATRIX LCD
S6B2104
Table 1. Pin Description (Continued) Pin No I/O Nam e Pin I/O Function SHL Display data shift direction Description Interface
EOB,EIB I/O (31,50)
EOB EIB
I O
L
D0: S1S5... S77 D1: S2S6... S78 D2: S3S7... S79 D3: S4S8... S80 D0: 80S76... S4 D1: 79S75... S3 D2: 78S74... S2 D3: 77S73... S1
Enable input terminal of S6B2104. Enable output terminal of S6B2104. EIB is connected to next S6B2104's EOB when the S6B2104's are connected in series (cascade connection). Enable input terminal of S6B2104. Enable output terminal of S6B2104. EOB is connected to next S6B2104's EIB when the S6B2104's are connected in series (cascade connection)
S73 S74 S75 S76 S77 S78 S79 S80 Shift DDDDDDDD 01230123 First Data Shift Shift Direction S73 S74 S75 S76 S77 S78 S79 S80 DDDDDDDD 01230123 D0 D1 D2 Last Data D3
EIB EOB
I O
H
D0-D3 (43-46)
EIB EIB
O
S1 S2 S3 S4 DDDD 0123 First Data
I
H
EOB
O
S1 S2 S3 S4 DDDD 0123
I
EOB
I
L
D0 Shift Direction D1 D2 Last Data D3
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S6B2104
80CH SEGMENT DRIVER FOR DOT MATRIX LCD
Display data input
Display data input pins for 4 bit parallel shift register and it is input synchronized with the clock pulse. The combination of D0-D3 level, M signal, display data output level and the display on the LCD panel is described on the table below. (DISPOFFB = H)
D0-D3 L H L H M L L H H Display Data Output Level V3 V1 V4 VEE Display on the LCD OFF ON OFF ON
Controller
NOTES: 1.
VDD C C C C C C R R V3 R V4 R V5 (to S6B0103) VEE V2 (to S6B0103) V1 VDD S1 - S80 To LCD Panel
S6B2104
VSS
V1, VEE V3, V4
Selected Level Nonselected Level
n = 5 (1/64 duty) to 13 (1/256 duty)
2.
M L L H H X
X: Don' care. t
Latched Data L H L H X
DISPOFFB H H H H L
Output level (S1- S80) V3 V1 V4 VEE V1
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80CH SEGMENT DRIVER FOR DOT MATRIX LCD
S6B2104
3.
- EOB and EIB pins works as input terminals. ENABLE F/F stops display data at "H" level input. ENABLE F/F starts display data at "L" level input. - EOB and EIB pins work as output terminals. These terminals are set to the "H" level immediately after ENABLE F/F is initialized by the load pulse. Upon completion of 80-bit serial/parallel conversion using the shift clock input from the CL2 terminal, these terminals are then set to the "L" level. - The operation of ENABLE F/F is terminated and held unchanged until the next load pulse is detected. (For cascade connection, refer to the application circuit drawing)
POWER DOWN FUNCTION
In order to reduce the power consumption, in case of cascade connection, S6B2104 has a "power down function". EIB EOB Enable input Enable output Enable Disable L H
EOB of Nth driver is connected to EIB of (N+1)th driver S6B2104
CL1 ~ ~ ~ ~ ~ ~ 1 CL2 ~~~ ~~~ ~~ ~~ ~~ ~~ 1st EIB (input) 1st EOB (output) ~ ~ ~ ~ Shift CL2 ~~ ~~ ~ ~ ~ ~ 2nd EIB (input) ~ ~ ~ ~ 2nd EOB (output) 1 Shift CL2 ~ ~ 2 ~ ~ 19 20 ~ ~ 2 19 20 1 2 19 20 20
SHL = H (EIB = Input, EOB = Output) First S6B2104' EOB should be connected to second S6B2104' EIB. s s
.
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S6B2104
80CH SEGMENT DRIVER FOR DOT MATRIX LCD
Timing Chart- 1/200 Duty, 1/15 Bias
200 CL1 Latched Data M
1
2
200
1
2
200
1
2
M CL1 D0 - D3 CL2 Latched Data
200 CL1 Latched Data M
VDD (V1) V2 V3
2
200
1
2
200
1
2
L
H
L
L
H
L
L
H
L
V4 V5 VEE (V6)
V1 = VDD V4 = VDD-8/10V
LCD
V2 = VDD-1/10V V5 = VDD-9/10V
LCD LCD
V3 = VDD-2/10V V LCD = VDDVEE
LCD
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